Complex integrated circuit designs such as microprocessors commonly use parity circuits as a means for error-checking various data manipulation and transfer operations. For example, parity circuits are used to check the results of logical operations (AND, OR, XOR), addition and shift operations, and transfers over internal or external data buses.
One common design for a parity circuit uses cross-coupled field effect transistors as shown in FIG. 1. In this design, two chains of transistors form a pair of legs arranged in parallel between a power source and a ground. Each transistor in one leg is cross-coupled to a corresponding transistor in the other leg by means of two cross-coupling transistors. Non-inverted data bits are applied to the gates of the leg transistors, while inverted data bits are applied to the gates of the cross-coupling transistors. The inputs act to enable two separate D.C. pathways within the parity circuit, the exact configuration of the pathways being a function of the states of the particular data bits so applied. One of the D.C. pathways will always extend from ground up to one of the parity output nodes, while the other D.C. pathway (the "charging path") will always extend from Vcc down through the other parity output node and ultimately to a floating termination near the end of one of the circuit legs.
In operation, newly-generated parity outputs become valid and stable only after ground voltage has propagated all the way up through the first pathway and after Vcc has propagated all the way down through the second pathway. Thus, response time depends on how quickly the power source can deliver sufficient current into the parity circuit in order to bring the output nodes to their steady-state voltage levels.
It is a specific object of the present invention to provide a cross-coupled parity circuit having better response time than conventional cross-coupled parity circuits, while not requiring a significant increase in layout area.